It would be desirable if the cross-coupling of output stages could create a high performance static latch in integrated MOS circuits as it does in discrete circuits. More particularly, if would be desirable if there were a static latch circuit configuration for super buffer output stages that provided fast rise times, a minimum of gate delay from input to output, an ability to drive heavy loads, and low internal power dissipation. A resistor would be the natural choice for a feedback element to use as coupling from the output of one stage to the input of the other. Risetime and power dissipation considerations favor a design wherein such resistive feedback is of a high ohmic value. Unfortunately, when rendered as MOS devices in an integrated circuit (IC), actual resistors in the tens or hundreds of kilo-ohm range are hundreds of times larger than MOS transistors. As a consequence, it is common for a high performance latch in an MOS IC to be a dynamic latch only, requiring that the output be periodically clocked back into the input to refresh the state of the latch.
According to the invention a depletion device is used to provide high-valued resistive feedback to form a high performance static super buffer latch in an MOS IC. Since the output stages are of the super buffer configuration, with the depletion loads driven by complementary inputs, the latch affords good speed and output power. As will be described, for either state of the latch only one load is on at any one time, so internal power dissipation is kept to a minimum. The invention is applicable to both N-channel and P-channel processes. The resulting latch can also be used as a stage in a static shift-register.